1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a shared sense amplifier type semiconductor memory device wherein a sense amplifier is shared by two sets of bit lines, and a method of operation thereof.
2. Description of the Background Art
FIG. 10 is a circuit diagram illustrating a configuration of a main part of a conventional shared sense amplifier type semiconductor memory device. This semiconductor memory device is of a configuration of folded bit lines.
Referring to FIG. 10, memory cell arrays la, lb are commonly provided with a group of sense amplifiers 2. Memory cell array 1a includes a plurality of bit line pairs, a plurality of word lines crossing these bit lines, and a plurality of memory cells MC provided at their cross-over points. Two sets of bit line pairs BL1, BL1 and BL3, BL3, and two work lines WL1, WL2 are shown in FIG. 10. Similarly, memory cell array 1b includes a plurality of bit line pairs, a plurality of word lines crossing these bit line pairs, and a plurality of memory cells MC provided at their cross-over points. Two sets of bit line pairs BL2, BL2 and BL4, BL4, and two word lines WL3, WL4 are shown in FIG. 10. Each memory cell MC comprises a dynamic MOS memory including a MOS transistor and a storage capacity connected in series.
A group of sense amplifiers 2 include a plurality of balance type flipflop sense amplifiers 20 each of which amplifies potential difference produced between bit lines of a bit line pair due to a charge amount of the memory cells MC. Bit line pair BL1, BL1 is connected to a sense node pair N1, N2 of sense amplifier 20 through a transmission transistor pair S11, S13 formed of two N channel MOS transistors. Bit line pair BL2, BL2 is connected to a sense node pair N1, N2 through a transmission transistor pair S12, S14 formed of two N channel MOS transistors.
Bit line pair BL1, BL1 is connected to an input/output line pair I/O, I/O through a transmission transistor pair T1, T2 formed of two N channel MOS transistors. Bit line pair BL2, BL2 is connected to an input/output line pair I/O, I/O through a transmission transistor pair T3, T4 formed of two N channel MOS transistors. An equalizing transistor Q1 formed of an N channel MOS transistor is connected between bit line BL1 and bit line BL1. An equalizing signal .phi..sub.EQ is applied to the gate of equalizing transistor Q1. A precharge electric potential V.sub.BL is applied to bit line BL1 through a precharge transistor Q2 formed of an N channel MOS transistor. A precharge signal .PHI..sub.PR is applied to the gate of precharge transistor Q2. Bit line pair BL2, BL2 is connected to equalizing transistor Q1 and precharge transistor Q2 in the same manner.
A bit line pair BL3, BL3 and a bit line pair BL4, BL4 are structured in the same manner as bit line pair BL1, BL1 and bit line pair BL2, BL2. Column selection signals CS1, CS2 are applied from a column decoder 4a to the gates of a transmission transistor pair T1, T2 corresponding to bit line pair BL1, BL1 and the gates of transmission transistor pair T1, T2 corresponding to bit line pair BL3, BL3, respectively. Column selection signals CS3, CS4 are applied from a column decoder 4b to the gates of a transmission transistor pair T3, T4 corresponding to bit line pair BL2, BL2 and the gates of a transmission transistor pair T3, T4 corresponding to bit line pair BL4, BL4, respectively.
A control signal .phi.1 is applied to the gates of transmission transistor pair S11, S13, and a control signal .phi.2 is applied to gates of transmission transistor pair S12, S14.
The above shared sense amplifier type semiconductor memory device is disclosed, for example, in Japanese Patent Laying-Open No. 63-2197.
Operation of the semiconductor memory device of FIG. 10, in particular, operation at the time of reading and refreshing will be described with reference to a signal waveform diagram in FIG. 11.
During a precharge period, control signals .phi.1 and .phi.2 attain high levels (power supply potential Vcc). As a result, transistors S11-S14 are turned on. Equalizing signal .phi..sub.EQ and precharge signal .phi..sub.PR attain high levels. As a result, transistors Q1, Q2 are turned on, and precharge electric potential V.sub.BL (normally 1/2.multidot.Vcc level) is supplied to bit line pairs BL1, BL1-BL4, BL4.
In a reading period, a row decoder (not shown) selects any of a plurality of word lines. Assuming that, for example, a word line WL1 is selected, at this time control signal .phi.1 maintains a high level, and control signal .phi.2 goes to a low level (ground potential). As a result, transistors S12, S14 are turned off. Information stored in memory cells MC connected to word line WL1 is read to corresponding bit lines BL1, BL3, respectively. As a result, potential differences are produced between bit line pair BL1 and BL1, and between bit line pair BL3 and BL3, respectively. Thereafter, when sense amplifiers 20 are activated, the potential differences are respectively amplified. Any of a plurality of column selection signals applied by column decoder 4a rises to a high level. For example, column selection signal CS1 attains a high level. As a result, a potential difference between bit line pair BL1 and BL1 is transmitted to an input/output input/output line pair I/O, I/O.
In a case where one of word lines within memory cell array 1b is selected, control signal .phi.1 goes to a low level and control signal .phi.2 maintains a high level. Apart from that, the operation is the same as the above operation.
In the above conventional shared sense amplifier type semiconductor memory device, two control signals .phi.1, .phi.2 having different waveforms are required in order to turn on either transmission transistors S11, S13 or transmission transistors S12, S14. As a result, a problem exists that the number of interconnections increases as the number and the area of control signal generation circuits increase.